LX1: a compact RV32IMC core built around verification and debug
A 3-stage in-order RV32IMC core with the extensions that make it useful in a real SoC — privilege, PMP, a debug module with JTAG, and an RVFI port for formal — at 3.50 CoreMark/MHz.
LX1 is a small RISC-V core, but "small" here means complete enough to be trusted, not stripped down. It's a 3-stage, in-order RV32IMC implementation with Zicsr and the Zba/Zbb/Zbs bit-manipulation extensions — the mix that makes compiled code compact and fast without ballooning the pipeline.
The parts that make it usable in an SoC
A core on its own isn't a system. LX1 includes the pieces you actually need to bring one up:
- M/U privilege modes and physical memory protection (PMP), so you can run separated user code with real memory isolation.
WFIand an in-core CLINT for timer and software interrupts — the interrupt story is built in, not bolted on.- A wait-state OBI bus, so it composes cleanly with memory and peripherals that aren't single-cycle.
Debug is a first-class feature
Bring-up without debug is guesswork. LX1 ships a full RISC-V Debug Module with a JTAG DTM, so you can halt, single-step, and inspect state with standard tooling from the first board bring-up — not something added later once the pain sets in.
Verification you can point to
The core exposes an RVFI commit port, which turns "does it execute RISC-V correctly?" into a checkable, formal property rather than a hope. That commit trace is the backbone of the verification story: every retired instruction is observable and can be checked against a reference.
And it performs
The extensions and pipeline earn their keep: 3.50 CoreMark/MHz and 1.25 DMIPS/MHz (Dhrystone). Respectable numbers for a 3-stage in-order design, and enough headroom for real embedded workloads.
The theme across LX1 is the same one that runs through the rest of my hardware work: correctness you can demonstrate. A commit port and a debug module aren't glamorous, but they're what let someone else adopt the core with confidence.