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Weaving an FPGA SoC from independently packaged IP

Why I compose SoCs from packaged IP into non-flattened, reviewable SystemVerilog — with a technology abstraction layer — instead of clicking through a block-diagram GUI.


Block-diagram SoC tools are wonderful until you need to diff a change, review it in a pull request, or bring the same system up on a second board. Then the generated netlist fights you: it's flattened, it's regenerated wholesale, and it doesn't read like the design you sketched on the whiteboard. Weft is my answer to that — a builder that assembles a system from a file and emits SystemVerilog you'd be happy to review.

Composition, not flattening

Weft takes independently packaged IP — a RISC-V core, an AXI crossbar, memory, peripherals — and weaves them into non-flattened SystemVerilog. The hierarchy survives generation. You can open the top level and see the system, and a change shows up as a small, legible diff instead of a regenerated wall of nets. The design stays a design, not a build artifact.

A technology abstraction layer

One system description should be able to target more than one FPGA family. Weft keeps the family-specific pieces — the primitives that don't port — behind an abstraction layer, so the same SoC can bring up on different silicon without rewriting the top. The first bring-up target is the Digilent Arty A7-100T (Artix-7), but the design isn't welded to it.

Packaging is the contract

The composition only works because the inputs are honestly packaged. Weft-soc handles that side: it weaves IP-XACT components into a design from a file, not a GUI. Each block declares its interfaces, registers, and parameters, and the builder connects them by contract. Swap a block for a better one and the integration story doesn't change — only the implementation behind the contract does.

Open first, commercial later

Bring-up uses open-source components so the whole system is inspectable end to end. Commercial IP can be added over time behind the same packaging interface — the seams stay in the same place. That's the point of building this way: the system is legible, portable, and reviewable, which is exactly what a block diagram gives up the moment it flattens.