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Notes on hardware design, SoC tooling, and AI research. Filter by topic below.

Jul 15, 2026HardwareRTLVerification

Designing reusable AXI4-Lite IP that drops into someone else's SoC

Reusability in hardware IP is mostly the work around the RTL: single-sourced registers, a contained vendor surface, checkable verification, and vendor-neutral packaging.

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Jul 12, 2026HardwareRISC-VVerification

LX1: a compact RV32IMC core built around verification and debug

A 3-stage in-order RV32IMC core with the extensions that make it useful in a real SoC — privilege, PMP, a debug module with JTAG, and an RVFI port for formal — at 3.50 CoreMark/MHz.

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Jul 8, 2026HardwareSoC

Weaving an FPGA SoC from independently packaged IP

Why I compose SoCs from packaged IP into non-flattened, reviewable SystemVerilog — with a technology abstraction layer — instead of clicking through a block-diagram GUI.

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Jul 2, 2026AIHardwareData

Machine learning on hardware: the SoC-Builder RTL dataset

A reproducible, machine-generated corpus of synthesizable SoC RTL — the data foundation for representation learning on hardware, and a step toward differentiable EDA.

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Jun 28, 2026AIDataNLP

Curating large multilingual corpora for language models

Lessons from building 100B-token corpora across Turkish, Dutch, Greek, and Bulgarian — and why, for smaller languages, the dataset work is most of the model work.

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