Projects
Everything I've built
Hardware IP and tooling, and AI models and datasets — grouped by area. Stats and READMEs are read directly from GitHub and Hugging Face, so every page is current.
aes
RTL & IPAES crypto core for FPGA — AES-128/192/256, encrypt and decrypt, FIPS-197 bit-exact, ECB/CTR/CBC/XTS/GCM.
uart
RTL & IPUART with AXI4-Lite CSRs for FPGA and ASIC — TX/RX FIFOs, programmable framing and baud rate, sticky error flags.
xbar
RTL & IPParameterized, general-purpose AXI4-Lite N×M crossbar and AXI4-Stream N×M switch for FPGA and ASIC.
ila
RTL & IPInternal logic analyzer with AXI4-Lite CSRs for FPGA and ASIC.
weft
SoCAn FPGA SoC builder — weaves independently packaged IP (a RISC-V core, an AXI crossbar, memory, peripherals) into clean designs.
weft-soc
SoCWeave IP-XACT components into SoC designs — from a file, not a GUI.
wavescope
ToolingA fast, modern waveform viewer for hardware engineers — VCD, FST, CSV, and SPICE in one tool.
matryoshka-embedding-v1
AI & MLMultilingual Matryoshka embedding model (XLM-RoBERTa) for sentence similarity and retrieval.
Lumees-3.8B-Reasoning
AI & MLA 3.8B-parameter reasoning-focused language model.
HK-362M
AI & MLA compact 362M-parameter language model for educational content.
reranker-Multilingual-MiniLM-L12-H384-msmarco-mse
AI & MLA multilingual MiniLM cross-encoder reranker trained on MS MARCO.
Datasets
Large multilingual corpora and training data, live from Hugging Face.