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FPGA SoC builder — weaves independently packaged IP into RISC-V systems.

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An FPGA SoC builder. It weaves independently packaged IP — a RISC-V core, an AXI crossbar, memory, peripherals — into clean, non-flattened SystemVerilog, with a technology abstraction layer so one design can target more than one FPGA family. Open-source components first; commercial IP added over time.

First bring-up target: Arty A7-100T (Artix-7).