xbar

A parameterized, general-purpose AXI4-Lite N×M crossbar and AXI4-Stream N×M switch for FPGA and ASIC — the interconnect that wires managers to peripherals when assembling an SoC. Plain synthesizable SystemVerilog with no vendor primitives, verified by constrained-random simulation against a scoreboard plus SymbiYosys proofs, and packaged as vendor-neutral IP-XACT 1685-2014.

Full design in docs/spec.md: interfaces, parameterization (NUM_M/NUM_S/address map), the transaction-latch + circuit-switched microarchitecture, round-robin arbitration with a proven fairness bound, the deadlock-freedom argument, integration notes, and how it's verified.

What's here

xbar_axil — AXI4-Lite N×M crossbar. Concurrent routing, round-robin arbitration with a proven fairness bound, per-manager transaction latch (one outstanding write + read), and a DECERR terminator for unmapped addresses. See docs/spec.md.
xbar_axis — AXI4-Stream N×M switch. TDEST-routed, packet-atomic (a connection locks to TLAST), with an always-ready sink that drops packets with an invalid destination and pulses bad_dest. See docs/spec_axis.md.

Both are plain synthesizable SystemVerilog, single clock domain, no vendor primitives, packaged as vendor-neutral IP-XACT.

Verification

Formal (SymbiYosys) — arbiter fairness (F1, widths 2/4/8), crossbar routing and payload (F2), safety and bounded completion (F3), and the stream switch (F4). Every proof is mutation-tested (e.g. a fixed-priority arbiter fails F1). make formal.
Constrained-random simulation — manager/subordinate BFMs against a scoreboard, swept over 1×1 / 1×4 / 2×2 / 4×2 / 2×4@DW64 plus 4-manager contention; the stream switch over 1×1 / 2×2 / 4×3 plus contention. 96.4% line coverage on rtl/ (the misses are unreachable defensive FSM defaults). make sim-all.
IP-XACT — 1685-2014 package for both components, schema-validated (ipxact/). make ipxact.

Integration test: make sim-aes puts a real AXI4-Lite peripheral — an AES crypto core, used here purely as an example subordinate — behind the crossbar and drives it end-to-end: key/IV programmed through the xbar, then NIST SP 800-38A CTR-AES128 vectors checked bit-exact, plus register readback, a DECERR access, and a concurrent memory subordinate (XBAR_AES P 0000). It needs that peripheral's repo checked out alongside (AES=<path> to point elsewhere); the goal is to exercise the crossbar against a genuine peripheral rather than a BFM.

On silicon: board-verified on the Arty A7-100T via an echo demo — an FSM AXI master programs a UART through this crossbar and 2000/2000 bytes round-trip over the physical USB-UART. (The board wrapper ships with the UART IP.)

Out-of-context implementation on xc7a100t-1 (Vivado 2026.1), 10 ns clock:

Top	Config	LUT / FF	WNS	Fmax
`xbar_axil`	2×4, DW=32	613 / 288	+4.96 ns	≈ 198 MHz
`xbar_axis`	2×2, DW=128	284 / 10	+6.43 ns	≈ 280 MHz

make lint       # Verilator -Wall, clean (both tops)
make sim        # quick 2x4 constrained-random run    -> "XBAR P 0000"
make sim-all    # axil config sweep + contention, then the axis sweep
make sim-axis   # stream-switch sweep + contention    -> "XBAR_AXIS P 0000"
make sim-aes    # AES IP behind the crossbar (needs ../aes) -> "XBAR_AES P 0000"
make coverage   # merged line coverage, rtl/ only
make formal     # F1 fairness + F2/F3 crossbar + F4 switch proofs (SymbiYosys)
make ipxact     # vendor-neutral IEEE 1685-2014 package (ipxact/)
make synth-ooc  # Vivado OOC synth+impl, timing-gated (synth-ooc-axis: switch)

Layout

rtl/     common/pkg.sv, axil/{decoder,txn_latch,rr_arb,decerr,xbar}.sv,
         axis/switch.sv (xbar_axis, shares the proven arbiter)
tb/      tb_xbar_rand.sv (constrained-random + full scoreboard + protocol
         checks + wait bounds) + BFMs; tb_xbar_axis.sv (packet atomicity/
         order/routing monitor) + source BFM; tb_xbar_aes.sv (integration)
formal/  xbar_arb.sby (F1), xbar_axil.sby (F2/F3), xbar_axis.sby (F4);
         harnesses are yosys-dialect Verilog -- sv2v strips assert/assume,
         so only the DUTs are flattened
docs/    spec.md (axil crossbar), spec_axis.md (stream switch)
gen/     ipxact_gen.py (IEEE 1685-2014, axil + axis components)
scripts/ coverage.sh
hw/tcl/  synth_ooc.tcl, synth_ooc_axis.tcl

What's here

Verification

Layout

License